AMD's EPYC Genoa-X CPUs with 3D V-Cache are expected to launch this year with large pools of cache alongside the Zen 4 cores. New information shows the exact amount of cache and clocks that we could expect from the upcoming server chips and the 2nd EPYC family with 3D V-Cache technology.
AMD EPYC Genoa-X Server CPUs Feature Over 1000 MB of Cache Thanks To 3D V-Cache Tech
According to a leaked spec sheet, we get to see details of two AMD EPYC Genoa-X CPUs which carry the same specs but one of them is an ES part "100-000000892-04" while the other is a retail sample "100-000000892-06". Both chips feature support on the SP5 socket and come in a "B1" revision. It's going to be a similar core configuration as the existing Genoa chips with 12 Zen 4 CCDs and a single I/O die but each of the Zen 4 CCDs will feature a 3D V-cache stack with up to 64 MB of L3 cache.
So for AMD's EPYC Genoa-X CPUs, that's 384 MB of L3 cache from the CCDs, 768 MB of L3 cache from the 3D V-Cache stacks, & 96 MB of L2 cache for a total of 1248 MB cache. There are also 3 MB of L1 cache (Instruction/data). This is 2.6x higher cache than the standard Genoa chips and also a 56% increase in cache amount versus the Milan-X (1st Gen EPYC 3D V-Cache chips). All chips will be rated at 400W with TDPs configurable down to 320W.
Coming to clock frequencies, it looks like the AMD EPYC Genoa-X chips will have a maximum clock frequency range of up to 3.7 GHz which is the same as the EPYC 9654 96-Core Genoa CPU. These chips also feature a peak thermal range of 100C. We already know of four EPYC Genoa-X SKUs as were leaked a while ago.
The top chip will be the EPYC 9684X with the max 96 core and 1152 MB of L3 cache. There will also be the EPYC 9384X with 32 cores, EPYC 9284X with 24 cores, and the EPYC 9184X with 16 cores. All chips will be positioned at cache-optimized workloads as was the case with the previous generation of 3D V-Cache EPYC CPUs. The AMD EPYC Genoa-X CPUs are expected to hit servers by the mid of 2023.
